1. Field of the Invention
This invention relates generally to logic circuits. More specifically, this invention is directed to a configuration of a logic cell that has reduced sensitivity to delay.
2. General Background and Description of Related Art
A Josephson junction is formed by creating a weak link (typically a tunnel junction) between two superconductors. The junction can switch between a superconducting state and a normal state over a time interval on the order of picoseconds. Since a change in the voltage across the junction accompanies this change in state, and the associated switching speed is much greater than that of a semiconducting junction, a significant potential exists for constructing superconducting logic circuits that operate much faster than semiconducting logic circuits.
A superconductor is an example of a macroscopic quantum system. As such, it can be described by a quantum mechanical wavefunction having a characteristic phase, xcfx86i. The current density within any quantum system is proportional to the gradient of the wavefunction and its complex conjugate thus making it a function of the spatial variation of xcfx86i. Since the two superconductors surrounding the Josephson junction have different phases (xcfx861 and xcfx862), they can be expected to generate a current flow across the junction as a function of their phase difference, xcfx86 (where xcfx86=xcfx861xe2x88x92xcfx862). Specifically, the superconducting current is given by,
IS=ICsinxcfx86(t) where dxcfx86/dt=2xcfx80V/"PHgr"0
"PHgr"0 is one quantum of magnetic flux (2.07xc3x9710xe2x88x9215 Wb), Ic is the junction""s critical current, and V is the voltage across the junction. Two types of currents across the junction are evident. A direct, nondissipative super-current flows for V=0, and a dissipative normal current flows for Vxe2x89xa00. In addition, for a changing V within the junction, there is the usual displacement current associated with a varying electric field. Adding all these components and writing V and the electric field in terms of xcfx86 gives for the total current,
I=Ic sinxcfx86(t)+("PHgr"0G/2xcfx80)dxcfx86/dt+("PHgr"0C/2xcfx80)d2xcfx86/dt2xe2x80x83xe2x80x83(1)
where G is the conductance across the junction and C is the capacitance of the junction. Writing this equation in terms of dimensionless variables gives,
i=sinxcfx86(xcfx84)+dxcfx86/dxcfx84+xcex2d2xcfx86/dxcfx842,
where
i=I/Ic, xcfx84=(2xcfx80Ic/"PHgr"0G)t and xcex2=2xcfx80IcC/"PHgr"0G2xe2x80x83xe2x80x83(2)
Equation 1 is similar to one describing a driven damped pendulum with I corresponding to the driving force, xcfx86 corresponding to the displaced angle of the pendulum, G corresponding to the damping force, and C corresponding to the inertial mass. With a suitable choice of G, the junction can be made to operate in a mode that is critically-damped, over-damped, or under-damped, just as in the case of the pendulum. In equation 2, xcex2 is known as the McCamber-Stewart parameter. The junction will be over-damped for xcex2 less than 1, and under-damped for xcex2 greater than 1.
An under-damped junction is said to be hysteretic because even after the total flow of current I, goes to zero (i.e. there is no driving force) xcfx86 still oscillates (due to the xe2x80x9cinertiaxe2x80x9d) giving rise to an alternating voltage across the junction that takes some time to damp out. Eventually the junction does latch within the superconducting state, but the associated time delay can be significant. When current is applied a similar oscillatory motion can occur before steady state equilibrium is reached.
There are two fundamental paradigms around which to construct Josephson junction logic circuits. The first is to view data in terms of the voltage state of the junction, in which case the logic circuits are designed to latch the junction in either the zero voltage state or in the non-zero voltage state. Since the non-zero voltage state requires a minimum conductance to prevent significant power consumption, and small G means small damping, such a voltage latching approach requires an under-damped (i.e. hysteretic) junction, which partially relinquishes the speed advantage of superconducting logic circuits. The other paradigm is to view data in terms of the fluxes of the magnetic fields (B-fields) produced by the superconducting currents circulating across the loops within the logic circuit. Since a voltage pulse is associated with the generation and transfer of these fluxes, it is the transition between voltage states and not the states themselves that is important, allowing the use of over-damped junctions (i.e. junction with a relatively large shunt conductance), and giving this approach a marked advantage over the latching approach.
In addition to being related to the voltage across the Josephson junction, xcfx86 is directly related to the flux of the magnetic field. Therefore, changes in xcfx86 are associated with changes in the magnetic flux as well as in changes in the voltage. However, since "PHgr"0 is the most elementary unit of magnetic flux, also known as a single flux quantum (SFQ), the change in xcfx86 must be sufficient to generate at least one SFQ to effect a change in the flux.
The SFQ approach to storing and manipulating data via under-damped Josephson junctions is known as Rapid Single Flux Quantum (RSFQ). A SFQ is generated by using a current to trigger a 2xcfx80 change in xcfx86 across an over-damped junction. Typically the junction is biased with a direct current just below Ic and then driven into the normal state (i.e. switched) with the addition of an input current (which sums the total current to above Ic). From (1) and the pendulum analogy this process is seen as analogous to maintaining the pendulum at just below the horizontal (xcfx86=xcfx80/2) and then kicking it up past the vertical with a sufficiently large input torque. The system then spontaneously rotates and, if sufficiently damped, returns just shy of its starting point after traversing essentially 2xcfx80 radians. The SFQ that results can be detected via its associated voltage pulse V(t), which is very short and of quantized area:
∫V(t)dt ="PHgr"0≈2.07 mVxc2x7ps
The SFQ can be allowed to dissipate out of the circuit or it can be trapped by allowing it to establish a persistent current within a superconducting loop having a stabilizing self-inductance (i.e. L≈"PHgr"0/I).
Typically, bit-wise logic functions are performed by synchronizing a predetermined interaction between SFQ pulses. Usually the time window within which the input pulses are constrained to appear at the pertinent Josephson junction is small enough to be considered simultaneous. Pulses arriving outside this time window will cause the junction to generate either no pulse, or, in the case of arrival times not very far outside this window, more than one pulse. Input delay insensitivity is a major factor determining the performance of superconducting logic circuits. And while a 300 GHz clock frequency is attainable, such circuits are extremely sensitive to input delay. The inability of a logic gate to process multiple input signals in parallel (i.e. independently of their arrival times) dramatically reduces the circuit operating frequency, and therefore its performance. Most RSFQ multi-polar circuits have this drawback; specifically that the input signals are required to arrive and/or prohibited from arriving simultaneously. It is therefore desirable to obtain a delay insensitive logic circuit that can process multiple input signals in parallel independently of their arrival times.
The invention provides a universal, delay-insensitive RSFQ logic cell having a first and a second Josephson input circuit with first and second data input lines respectively. Each input circuit contains a plurality of Josephson elements arranged to generate a SFQ pulse and sustain an associated SFQ persistent current in response to an input signal applied to its respective data input line. First and a second Josephson clock circuits are provided with respective first and second clock input lines. Each clock circuit includes a plurality of Josephson elements arranged to generate a SFQ clock pulse in response to an input signal applied to its respective clock input line. The first Josephson clock circuit is arranged to be in electrical contact with the first Josephson input circuit such that a portion of the SFQ persistent current from the first input circuit combines with a portion of the SFQ clock pulse from the first clock circuit to trigger the generation of a first SFQ output pulse. The second Josephson clock circuit and the second Josephson input circuit are connected similarly to the first clock and input circuits. The first Josephson input circuit is arranged to be in electrical contact with the second Josephson input circuit so that a portion of the SFQ current from the first data circuit combines with a portion of the SFQ current from the second data circuit such as to trigger the generation of a third SFQ output.
The universal logic cell can be configured to perform various digital/logical functions. For example, by merging various inputs and outputs the universal cell can be configured to be a delay-insensitive half-adder. One output provides a logical AND, and a combination of the other two outputs provide an exclusive OR. The universal cell can also be configured to provide a D flip-flop with complementary outputs.